The invention relates generally to processes for manufacturing an integrated circuit device and for manufacturing at least one tier (or layer) of such a device. More specifically, the invention relates to processes for forming patterned layers of (low dielectric constant) insulating materials using a stamping process, in which the dielectric layer may be formed, for example, from organosilicate or organic polymer material (or oligomeric precursors).
There is a ongoing desire in the microelectronics industry to increase the circuit density in multilevel integrated circuit devices (e.g., memory and logic chips), thereby increasing their performance and reducing their cost. Accordingly, there is a trend to not only reduce the minimum feature size on the chip (e.g., the circuit linewidth), but also to decrease the dielectric constant of the dielectric material interposed between chip features, thereby permitting closer spacing of the circuit lines without leading to an undesirable increase in crosstalk and capacitive coupling. In addition, there is a desire in the industry to reduce the dielectric constant of the materials utilized in the back end of the line (BEOL) portion of integrated circuit devices, which contain input/output circuitry, in order to reduce the requisite drive current and power consumption of the device. The most commonly used dielectric is silicon dioxide, which has the requisite mechanical and thermal properties to withstand the processing operations and thermal cycling associated with semiconductor manufacturing. However, silicon dioxide has a dielectric constant of about 4.0; dielectric materials having a dielectric constant of 3.0 or less would be preferred.
One class of materials that has been used as a dielectric is the polysilsesquioxane family of materials, also known as spin-on-glasses (SOG). These materials offer ease of processing: a thin film of such a material can be spun from solution onto a substrate, followed by thermal curing of the film to effect solvent removal and croslinking, thereby resulting in a solid phase dielectric film on the substrate. One complication with using SOG to produce dielectric layers is that fabricating thin wiring within a dielectric thin film is generally complex. Creating even a one-layer metal/dielectric structure may involve a multistep process. See, for example, U.S. Pat. No. 6,143,643 to Carter et al., in which the SOG composition is coated on a substrate and then cured, a photoresist is applied over the cured composition, photolithography is employed followed by selective etching of the photoresist, and metal is deposited followed by chemical/mechanical processing of the metal.
Another class of useful dielectric materials includes polyimides, polybenzoxazoles, and other high temperature thermosets (e.g., Dow Chemical Company""s SiLK brand of semiconductor dielectric resin). Polyimides are particularly useful as an interlayer dielectric material for insulating the conductor wiring interconnecting the chips on a multichip module, a process known as xe2x80x9cthin filmxe2x80x9d wiring. Multichip modules represent an intermediate level of packaging between the chips and the circuit board, and are made up of multiple layers of power, signal, and ground planes that deliver power to the chips and distribute the input/output signals between chips on the module or to and from the circuit board. Polyimides are attractive since they usually have dielectric constants of about 3.0-3.8 and mechanical and thermal properties sufficient to withstand the processing operations (including the thermal cycling) associated with semiconductor manufacturing.
Generally, the state of the art related to the fabrication of integrated circuits entails a series of complex optical lithography steps. Although efforts are underway to employ contact printing methods in the field of microelectronics, much of this effort has dealt with the printing of resist materials. (See, for example, PCT WO 00/54107A1 to Willson et al.) A general process of forming heterogeneous structures using stamping techniques has been disclosed in PCT WO 01/20402 to Jacobson et al. However, this reference does not teach, for example, how to form integrated circuit devices having low dielectric materials.
There remains a need for a versatile and efficient xe2x80x9cstampingxe2x80x9d process to produce low dielectric constant insulating materials in an integrated circuit, especially in view of the usefulness of dielectric materials to so many aspects of integrated circuits, including chips (e.g., chip back end of line, or xe2x80x9cBEOLxe2x80x9d), thin film packages, printed circuit boards, dielectric interlayers, passivation layers, alpha particle barriers, and stress buffers. Such a process would ideally permit an increase in manufacturing throughput while reducing cost.
One preferred implementation of the invention is a process for forming a layer of an integrated circuit that includes low dielectric constant material. Another preferred implementation of the invention is a process for forming a multi-tier integrated circuit device that includes (i) a substrate, (ii) interconnecting metallic circuit lines positioned on (or even within) the substrate, and (iii) low dielectric constant material in contact with the circuit lines (e.g., over and/or between the circuit lines). The dielectric material preferably comprises a porous material that has been patterned by a stamping process. Such a porous dielectric material has a dielectric constant lower than the analogous non-porous material. Accordingly, there is disclosed herein an improved process for the fabrication of integrated circuits that involves the pattering of dielectric material.
One implementation of the invention is a process for forming a portion of an integrated circuit. The process includes positioning a layer of material on a substrate, in which the material includes a polymeric composition and a decomposable (sacrificial) polymer. A patterned stamp is brought into contact with the layer to mold the layer, and then the stamp is removed from the molded layer, thereby leaving a pattern in the molded layer. By decomposing the sacrificial polymer, porous dielectric material is formed. The process also includes depositing metal onto the patterned layer and planarizing the metal to form a portion of an integrated circuit. In one preferred implementation, the molding includes inducing a chemical change in the polymeric composition, and the polymeric composition may advantageously include a precursor to dielectric material. In a preferred implementation, the sacrificial polymer is decomposed while the stamp is in contact with the molded layer. In another preferred implementation, the metal is planarized to form a tier of an integrated circuit, and the process is repeated to form one or more additional tiers of an integrated circuit.
Another implementation of the invention is a process for forming a portion of an integrated circuit. The process includes positioning a layer of material on a substrate, in which the material includes a precursor to a dielectric composition and a decomposable (sacrificial) polymer. The process further includes bringing a patterned stamp in contact with the layer to mold the layer and curing the precursor to the dielectric composition, thereby forming a molded layer of dielectric material. The process also includes removing the stamp from the molded layer of dielectric material, thereby leaving a pattern in the molded layer, and decomposing the sacrificial polymer to form porous dielectric material. A portion of an integrated circuit is then formed by depositing metal onto the patterned layer and planarizing the metal. In one implementation of the process, the curing includes heating the material while the material is in contact with the stamp. The dielectric composition may include an inorganic polymeric material or an organic polymeric material. In a preferred implementation of the process, the sacrificial polymer is decomposed while the stamp is in contact with the molded layer. The process advantageously further includes planarizing the metal to form a tier of an integrated circuit, and the process may be repeated to form a second tier of an integrated circuit, in which the second tier is adjacent to the first tier.
Yet another implementation of the invention is a process for forming a portion of an integrated circuit. The process includes positioning a layer of material on a substrate, contacting the material with a surface having relief structures therein, and imparting a pattern to the material through this contact to form a patterned layer, wherein the pattern is determined by the relief structures. The process further includes decomposing a sacrificial polymer present in the material to form porous dielectric material and depositing metal onto the patterned layer to form a portion of an integrated circuit. The material may include a precursor to a dielectric composition and may further include a solution in which a polymeric composition is present.
Still another implementation of the invention is an improved method for forming an integrated circuit, in which the improvement includes using a patterned stamp to form a molded layer of dielectric material, and then decomposing a sacrificial polymer within the layer to form porous dielectric material.
A more complete description of the invention is presented in the detailed description and the accompanying drawings.